amd64 is what happens when you take a 1978 instruction set, widen the registers, add a compatibility mode and promise never to break anything. That promise is the entire product. It is also the reason every x86 CPU is carrying four decades of decoder logic so your binary from 2009 can still run.

The decode tax

x86 instructions are variable length. The decoder does not know where the next instruction starts until it has decoded the current one. Modern cores work around this with a micro-op cache and aggressive prediction, but the work is still there, every cycle, on every core. Fixed-width instruction sets get to skip that party.

The x86 front endbytesvariable lengthtranslatecacheschedulecache missFetchInstruction QueueDecoderMicro OpsMicro Op CacheExecutionFast Path
The x86 front endFind the instruction, decode the instruction, translate it, then maybe execute it.

Diagram: The x86 front end. Fetch connects to Instruction Queue (bytes). Instruction Queue connects to Decoder (variable length). Decoder connects to Micro Ops (translate). Micro Ops connects to Micro Op Cache (cache). Micro Op Cache connects to Execution (schedule). Decoder connects to Fast Path and fails (cache miss).

Microcode is a patch channel

When the hardware has a correctness or security bug, the fix arrives as a microcode update. The instruction set you compiled against is not quite the instruction set the CPU actually implements. Spectre and Meltdown turned this from an obscure detail into a permanent mitigation tax.

The microcode patch pathsigned blobapply at bootnew behaviourinvalidslowerVendorMicrocode UpdateCPUModified SemanticsOld BenchmarkSecurity Mitigation
The microcode patch pathThe CPU ships with bugs and a mechanism to replace its own behaviour later.

Diagram: The microcode patch path. Vendor connects to Microcode Update (signed blob). Microcode Update connects to CPU (apply at boot). CPU connects to Modified Semantics (new behaviour). Modified Semantics connects to Old Benchmark and fails (invalid). CPU connects to Security Mitigation asynchronously (slower).

Segmentation is still in the silicon

The original 8086 had segment registers because it had 16-bit addresses and needed to reach 20 bits of memory. amd64 kept the segment registers in long mode mostly as a compatibility fiction. The descriptor tables, the privilege rings and the legacy modes are still there, still specified, still implemented. Nobody is removing them because something might depend on them.

Sixteen registers is a punchline

The original x86 had eight general-purpose registers. amd64 doubled that to sixteen. Compilers have been spilling registers ever since. AVX-512 added thirty-two vector registers and a frequency penalty, then some CPUs removed it again. APX is the current attempt to add more registers without breaking the encoding. The instruction set is a renovation project where every new room is built through the old kitchen.

The compatibility taxretainedretainedoptionalmust not breakmore workLegacy ModeProtected ModeLong ModeNew ExtensionOld BinaryDecoder
The compatibility taxEvery feature is optional, every mode is retained, every decoder pays for all of it.

Diagram: The compatibility tax. Legacy Mode connects to Protected Mode (retained). Protected Mode connects to Long Mode (retained). Long Mode connects to New Extension (optional). New Extension connects to Old Binary and fails (must not break). Old Binary connects to Decoder asynchronously (more work).

The museum is open

amd64 is not going anywhere. The ecosystem is too large, the toolchains too mature, the binaries too numerous. That is not a technical argument. It is an archaeological one. We are not using amd64 because it is good. We are using it because it is there, and because replacing it would mean recompiling the world.

The instruction set is a monument. Monuments are impressive. They are also not where you want to live.